1. Field of the Invention
The present invention relates to the semiconductor manufacturing process, and more particularly, to a method of manufacture that reduces charge loss in a nonvolatile memory cell and the structure thereof.
2. Description of the Related Art
Nonvolatile memory cell arrays such as EPROMs, FLASH EPROMs and EEPROMs have gained widespread acceptance in the industry. Nonvolatile memory cells do not require the periodic reflesh pulses needed by the capacitive storage elements of conventional one-device dynamic random access memory (DRAM) cells. This presents appreciable power savings. Because they rely upon charge injection/removal to establish the stored logic state, the write cycles of nonvolatile memory cells are appreciably longer than those of DRAM's.
It has been observed that there are data retention problems in nonvolatile memory cell arrays. It has been postulated that the poor data retention is due to mobile ions such as Na+, K+, or the like that approach the floating gate in the nonvolatile memory cell and cause the charge on the floating gate to be lost. For example, an inter-layer dielectric (ILD) layer (of a high dielectric reflowable material such as phosphosilicate glass or borophosphosilicate glass) is formed on the wafer. The manufacturing process for forming the ILD layer, such as deposition, photolithography and etching, causes the mobile ions to be introduced to approach the floating gate in the nonvolatile memory cell, seriously affecting device reliability.
FIG. 1 shows a structure 100 of a traditional flash memory cell, comprising a silicon substrate 110 whereon a gate structure 120 is formed. Silicon oxide spacers 130 are formed on the sides of the gate structure 120. A source region 140 and a drain region 150 are separately formed in the substrate 100 on either side of the gate structure 120. Moreover, the gate structure 120 comprises a tunnel oxide layer 122 formed on part of the substrate 110. A floating gate 124 is formed on the tunnel oxide layer 122, an inter-gate dielectric layer 126 on the floating gate 124, and a control gate 128 on the inter-gate dielectric layer 126.
Since silicon oxide layers cannot effectively stop the diffusion of mobile ions, the traditional structure 100 with silicon oxide spacers 130 cannot solve the problem mentioned previously.